Low-power bulk-driven time-domain comparator with high voltage-to-time gain for ADC applications

Author:

Sanati Roohollah,Khatib FarzanORCID,Javadian Sarraf Mohammad,Kardehi Moghaddam Reihaneh

Publisher

Elsevier BV

Subject

General Engineering

Reference24 articles.

1. A 0.3 V 8-bit 8.9 fJ/con.-step SAR ADC with sub-DAC merged switching for bio-sensors;Guo;Microelectron. J.,2017

2. A 16-bit calibration-free SAR ADC with binary-window and capacitor-swapping DAC switching schemes;Chung;IEEE Transactions on Circuits and Systems I: Regular Papers,2021

3. A 14-bit 40-MS/s Split-DAC based SAR ADC in 65 nm CMOS;Liang;Microelectron. J.,2022

4. A high accuracy sample and hold circuit with reduced non-linearity errors for SAR ADC in 45nm CMOS process;Velagaleti,2019

5. Energy-efficient switching scheme for SAR ADC with only two reference voltages;Liu;Analog Integr. Circuits Signal Process.,2018

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1. A Novel Design Method for 4-bit Absolute-Value Detector;Highlights in Science, Engineering and Technology;2022-12-27

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