A 14-bit 40-MS/s Split-DAC based SAR ADC in 65 nm CMOS

Author:

Liang Wenjie,Duan QuanzhenORCID

Funder

National Natural Science Foundation of China

Publisher

Elsevier BV

Subject

General Engineering

Reference18 articles.

1. Weaver Skyler and Moon Un-ku, “A 30% beyond VDD Signal Swing 9-ENOB Pipelined ADC Using a 1.2-V 30dB Loop-Gain Opamp;Gregoire,2011

2. A third-order DT △Σ modulator using noise-shaped Bi-directional single-slope quantizer;Maghari;IEEE J. Solid State Circ.,2011

3. A 4-bit, 1.6 GS/s low power flash ADC, based on offset calibration and segmentation;Chahardori;IEEE Trans. Circuits Syst. I: Reg. Pap.,2013

4. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure;Liu;IEEE J. Solid State Circ.,2010

5. A 12-bit, 45-MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration;Liu;IEEE J. Solid State Circ.,2011

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