Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture

Author:

Rajput Anil Kumar,Pattanaik Manisha,Kaushal Gaurav

Funder

Science and Engineering Research Board

Department of Science and Technology, Ministry of Science and Technology, India

Publisher

Elsevier BV

Subject

General Engineering

Reference33 articles.

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4. Y. Ma, Y. Du, L. Du, J. Lin, Z. Wang, In-Memory Computing: The Next-Generation AI Computing Paradigm, in: Proceedings of the 2020 on Great Lakes Symposium on VLSI, 2020, pp. 265–270.

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1. An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor;Memories - Materials, Devices, Circuits and Systems;2023-10

2. Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation;Microelectronics Journal;2023-07

3. Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array;IEEE Journal on Emerging and Selected Topics in Circuits and Systems;2023-03

4. An Energy-Efficient Hybrid SRAM-Based In-Memory Computing Macro for Artificial Intelligence Edge Devices;Circuits, Systems, and Signal Processing;2023-01-14

5. An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture;2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID);2023-01

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