Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation-Reference-Cited by-同舟云学术

Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation

Published:2023-07 Issue: Volume:137 Page:105795
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Rajput Anil Kumar^ORCID,Pattanaik Manisha

Funder

Ministry of Electronics and Information technology

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

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3. An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor;Memories - Materials, Devices, Circuits and Systems;2023-10

4. In-Memory Computing with 6T SRAM for Multi-operator Logic Design;Circuits, Systems, and Signal Processing;2023-08-19