Author:
Ramakrishnan V.N.,Srinivasan R.
Funder
Defence Research and Development Organisation
Reference15 articles.
1. SEU reliability analysis of advanced deep-submicron transistors–introduction;Jain;IEEE Trans. Device Mater. Relia.,2005
2. Kartik Mohanram, Simulation of transients caused by single-event upsets in combinational logic, in: Proceedings of the International Test Conference, Paper 37.3, 2005.
3. 〈http://public.itrs.net〉
4. Chen changqing, E. Er, Soh Ping Neo, Loh Sock Khim, Wang Qingxiao, J. Teong, Failure Analysis of 65nm Technology Node SRAM, Physical and Failure Analysis of Integrated Circuits, pp. 1–4, 2008.
5. Soft errors in advanced computer systems;Baumann;IEEE Des. Test Comput.,2004
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