The synergistic design of 5 V ESD protection applications using two holding voltage improving methods-Reference-Cited by-同舟云学术

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The synergistic design of 5 V ESD protection applications using two holding voltage improving methods

Published:2024-09 Issue: Volume:151 Page:106348
ISSN:1879-2391
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Ji Shuoxin,Wang Yang^ORCID,Yang Hongjiao,Su Haiping,Deng Zhiqin

Publisher

Elsevier BV

Reference27 articles.

1. A novel dual-directional DTSCR in twin-well process for ultra-low-voltage ESD protection;Gu;Solid State Electron.,2024

2. Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit;Hou;Jpn. J. Appl. Phys.,2024

3. Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices;Semenov;Microelectron. J.,2006

4. A low-voltage triggering SCR for on-chip ESD protection at Output and input pads;Chatterjee;IEEE Electron. Device Lett.,1990

5. ESD protection design with diode-triggered quad-SCR for separated power domains;Chen;IEEE Trans. Device Mater. Reliab.,2019

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