Author:
Sagahyroon Assim,Aloul Fadi A.
Reference36 articles.
1. A. Biere, B. A. Cimatti, E. Clarke, M. Fujita, Y. Zhu, Symbolic model checking using SAT procedures instead of BDDs, in: Proceedings of the Design Automation Conference (DAC), 1999, pp. 317–320.
2. G. Nam, F.A. Aloul, K.A. Sakallah, R. Rutenbar, A comparative study of two boolean formulations of FPGA detailed routing constraints, in: Proceedings of the International Symposium on Physical Design (ISPD), 2001, pp. 222–227.
3. F.A. Aloul, A. Ramani, I.L. Markov, K.A. Sakallah, generic ILP versus specialized 0–1 ILP: an update, in: Proceedings of the International Conference on Computer-Aided Design (ICCAD), 2002, pp. 450–457.
4. S. Memik, F. Fallah, Accelerated boolean satisfiability-based scheduling of control/data flow graphs for high-level synthesis, in: Proceedings of the International Conference on Computer Design (ICCD), 2002.
5. P. Bjesse, K. Claessen, SAT-based verification without state space traversal, in: Proceedings of Formal Methods in Computer-Aided Design (FMCAD), 2000, pp. 372–389.
Cited by
14 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献