SAT Based Scheduling in High Level Synthesis

Author:

Kundu Sudeshna,Chandrakar Khushbu,Roy Suchismita

Publisher

Springer International Publishing

Reference17 articles.

1. Gajski, D., Dutt, N., Wu, A.H., Lin, S.L.: High-level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers (1992)

2. Baruch, Z.: Scheduling algorithms for high-level synthesis. ACAM Scientific Journal 5(1-2), 48–57 (1996)

3. Hwang, C.T., Lee, J.H., Hsu, Y.C.: A formal approach to the scheduling problem in high level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10(4), 464–475 (1991)

4. Chaudhuri, S., Walker, R.: Ilp-based scheduling with time and resource constraints in high level synthesis. In: VLSI Design, pp. 17–20 (1994)

5. Memik, S., Fallah, F.: Accelerated sat-based scheduling of control/data flow graphs. In: IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 395–400 (2002)

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