1. Wang, C.-Y., Roy, K., Chou, T.-L.: Maximum power estimation for sequential circuits using a test generation based technique. In: Proceedings of the IEEE 1996 Custom Integrated Circuits Conference, pp. 229–232 (May 1996)
2. Hsiao, M.S., Rudnick, E.M., Patel, J.H.: Effects of Delay Models on Peak Power Estimation of VLSI Sequential Circuits. In: International Conference on Computer Aided Design, pp. 45–51. IEEE (1997)
3. Sagahyroon, A., Aloul, F.A.: Using SAT based technique in low power state assignment. Journal of Circuits, Systems, and Computers 20(8), 1605–1618 (2011)
4. Pedram, M.: Power minimization in IC Design: Principles and Applications. ACM Transactions on Desing Automation of Electronics System 1, 3–56 (1996)
5. Devadas, S., Keutzer, K., White, J.: Estimation of power dissipation in CMOS combinational circuits. In: Proceedings of the IEEE 1990 Custom Integrated Circuits Conference, pp. 19.7/1 –19.7/6 (May 1990)