An analysis of interconnect delay minimization by low-voltage repeater insertion-Reference-Cited by-同舟云学术

An analysis of interconnect delay minimization by low-voltage repeater insertion

Published:2007-04 Issue:4-5 Volume:38 Page:649-655
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Chandel Rajeevan,Sarkar S.,Agarwal R.P.

Publisher

Elsevier BV

Subject

General Engineering

Reference24 articles.

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5. Y.I. Ismail, E.G. Friedman, Optimum repeater insertion based on a CMOS delay model for on-chip RLC interconnect, Proc. IEEE ASIC (1998), pp. 369–373.

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