High-speed and low-power repeater for VLSI interconnects
Author:
Publisher
IOP Publishing
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
http://stacks.iop.org/1674-4926/38/i=10/a=105006/pdf
Reference29 articles.
1. VLSI scaling methods and low power CMOS buffer circuit
2. A power-optimal repeater insertion methodology for global interconnects in nanometer designs
3. Buffer insertion for noise and delay optimization
4. A distinctive O(mn) time algorithm for optimal buffer insertions
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