High Performance Buffer with Body Biasing Technique
Author:
Publisher
Springer Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-15-8221-9_299
Reference15 articles.
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3. Banerjee K, Mehrotra A (2002) A power-optimal repeater insertion methodology for global interconnects in Nanometer designs. IEEE Trans Electron Devices 49(11):2001–2007
4. Mehri M, Kouhani MHM, Masoumi N, Sarvari R (2013) New approach to VLSI buffer modeling, considering overshooting effect. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(8):1568–1572
5. Chandel R, Sarkar S, Agarwal RP (2005) Repeater insertion in global interconnects in VLSI circuits. Microelectron Int 22(1):43–50
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