Optimization of CMOS repeater driven interconnect RC line using genetic algorithm-Reference-Cited by-同舟云学术

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Optimization of CMOS repeater driven interconnect RC line using genetic algorithm

Published:2017-03-31 Issue:2 Volume:22 Page:167-172
ISSN:1007-1172
Container-title:Journal of Shanghai Jiaotong University (Science)
language:en
Short-container-title:J. Shanghai Jiaotong Univ. (Sci.)

Author:

Kaur Jasmeet,Gill Sandeep Singh,Kaur Navneet

Publisher

Springer Science and Business Media LLC

Subject

Multidisciplinary

Link

http://link.springer.com/content/pdf/10.1007/s12204-017-1817-5.pdf

Reference21 articles.

1. BANERJEE K, MEHROTRA A. A power-optimal repeater insertion methodology for global interconnects in nanometer designs [J]. IEEE Transactions on Electron Devices, 2002, 49(11): 2001–2007.

2. CHANDEL R, SARKAR S, AGARWAL R P. An analysis of interconnect delay minimization by low-voltage repeater insertion [J]. Microelectronics Journal, 2007 38: 649–655.

3. HAVEMANN R H, HUTCHBY J A. Highperformance interconnects: An integration overview [J]. Proceedings of the IEEE, 2001, 89(5): 586–601.

4. ADLER V, FRIEDMAN E G. Repeater design to reduce delay and power in resistive interconnects [J]. IEEE Transactions on Circuits and Systems. II: Analog and Digital Signal Processing, 1998, 45(5): 607–616.

5. RABEY J M. Digital integrated circuits: A design perspective [M]. 2nd ed. India: Prentice Hall of India, 2002: 134–172.

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