Author:
Amat E.,Almudéver C.G.,Aymerich N.,Canal R.,Rubio A.
Funder
European TRAMS project
Spanish MICINN
2012 Intel Early Career Faculty Honor program
Reference18 articles.
1. CMOS 6-T SRAM cell design subject to ‘atomistic’ fluctuations;Cheng;Solid-State Electron.,2007
2. W.K. Luk, J. Cai, R.H. Dennard, M.J. Immediato, S. Kosonocky, A 3-Transistor DRAM Cell with Gated Diode for Enhanced Speed and Retention Time. Symposium on VLSI Circuits, 2006, pp. 184–185.
3. Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data cache to combat process variability;Liang;IEEE Micro,2008
4. K. Lovin, B.C. Lee, X. Liang, D. Brooks, G.-Y. Wei, Empirical performance models for 3T1D memories, in: Proceedings of the IEEE International Conference on Computer Design, 2009, pp. 398–403.
5. X. Liang, R. Canal, G.-Y. Wei, D. Brooks, Process variation tolerant 3T1D-based cache architectures, in: IEEE/ACM International Symposium on Microarchitecture, 2007, pp. 15–26.
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