Random Pattern Generation and Redundancy Analysis in Memories
Author:
Affiliation:
1. Karunya Institute of Technology and Sciences, CBE, IN,Department of ECE
2. Karunya Institute of Technology and Sciences, CBE, IN,Department of EEE
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9787399/9787559/09787595.pdf?arnumber=9787595
Reference23 articles.
1. Efficient System-Level Hardware Synthesis of Dataflow Programs Using Shared Memory Based FIFO
2. Dual-Data Rate Transpose-Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems
3. A novel design of memristor-based bidirectional associative memory circuits using Verilog-AMS
4. Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22nm
5. Object-Level Memory Allocation and Migration in Hybrid Memory Systems
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