Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support-Reference-Cited by-同舟云学术

Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support

Published:2013-05 Issue:5 Volume:44 Page:421-430
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Jaiswal Manish Kumar,Cheung Ray C.C.

Publisher

Elsevier BV

Subject

General Engineering

Reference45 articles.

1. O. Storaasli, R.C. Singleterry, S. Brown, Scientific computation on a NASA reconfigurable hypercomputer, in: MAPLD International Conference, September 2002.

2. K. Underwood, FPGAs vs. CPUs: trends in peak floating-point performance, in: Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays ser. FPGA '04, ACM, New York, NY, USA, 2004, pp. 171–180.

3. FPGA-based high-performance and scalable block LU decomposition architecture;Jaiswal;IEEE Trans. Comput.,2012

4. G. Zhi, N. Walid, V. Frank, V. Kees, A quantitative analysis of the speedup factors of FPGAs over processors, in: Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays (FPGA-04), ACM, New York, NY, USA, 2004, pp. 162–170.

5. H. Parizi, A. Niktash, A. Kamalizad, N. Bagherzadeh, A reconfigurable architecture for wireless communication systems, in: Third International Conference on Information Technology: New Generations, vol. 0, 2006, pp. 250–255.

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