Impact of interface trap charge and temperature on the performance of epitaxial layer tunnel field effect transistor-Reference-Cited by-同舟云学术

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Impact of interface trap charge and temperature on the performance of epitaxial layer tunnel field effect transistor

Published:2022-02 Issue: Volume:120 Page:105348
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Debnath Radhe Gobinda^ORCID,Baishya Srimanta

Publisher

Elsevier BV

Subject

General Engineering

Reference46 articles.

1. Tunnel field Effect Transistor as energy-efficient electronic switches;Ionescu;Nature,2011

2. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec;Choi;IEEE Electron. Device Lett.,2007

3. Heteromaterial gate tunnel field effect transistor with lateral energy band profile modulation;Cui;Appl. Phys. Lett.,2011

4. Tunnel FET technology : a reliability perspective;Datta;Microelectron. Reliab.,2014

5. Double-gate tunnel FET with high-k gate dielectric;Boucart;IEEE Trans. Electron. Dev.,2007

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1. Unveiling the influence of temperature and interface traps on the performance of source-all-around vertical TFET;Microelectronics Journal;2024-06

2. A temperature dependent drain current model of P+ SiC GAA JLFETs for enhanced analog/RF performance;Micro and Nanostructures;2024-04

3. Noise Behavior and Reliability Analysis of Epitaxial Layer Encapsulated TFET for Different Source Materials;Handbook of Emerging Materials for Semiconductor Industry;2024

4. An analytical model for P+ pocket SiC gate all around Junctionless field effect transistor with impact of high temperature;Micro and Nanostructures;2023-10

5. Performance analysis of short channel effects immune JLFET with enhanced drive current;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2023-03-19

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