Current-integrating summer for DFE receiver with low common mode variation
Author:
Publisher
Elsevier BV
Subject
General Engineering
Reference20 articles.
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1. A two-stage slicer employing body biasing for 64-Gb/s PAM4 wireline receiver in 22-nm FDSOI technology;Microelectronics Journal;2024-09
2. A 16-Gb/s 3-tap adaptive DFE in 12-nm FinFET CMOS technology;Microelectronics Journal;2024-07
3. 6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS;IEICE Electronics Express;2022-11-25
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