A novel recessed-source negative capacitance gate-all-around tunneling field effect transistor for low-power applications-Reference-Cited by-同舟云学术

A novel recessed-source negative capacitance gate-all-around tunneling field effect transistor for low-power applications

Published:2024-03 Issue: Volume:145 Page:106126
ISSN:1879-2391
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Wei Weijie^ORCID,Lü Weifeng,Han Ying,Zhang Caiyun,Chen Dengke

Funder

National Natural Science Foundation of China

Zhejiang Province Natural Science Foundation

Publisher

Elsevier BV

Reference34 articles.

1. A tunnel FET for VDD scaling below 0.6 V with a CMOS-comparable performance;Asra;IEEE Trans. Electron. Dev.,2011

2. Nanowire tunnel FET with simultaneously reduced subthermionic subthreshold swing and off-current due to negative capacitance and voltage pinning effects;Saeidi;Nano Lett.,2020

3. Tunnel field-effect transistors as energy-efficient electronic switches;Ionescu;Nature,2011

4. Ferroelectric gating of two-dimensional semiconductors for the integration of steep-slope logic and neuromorphic devices;Kamaei;Nature Electronics,2023

5. Simple Ge/Si bilayer junction-based doping-less tunnel field-effect transistor;Kim;Nanotechnology,2022

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Performance evaluation of GPVs in existing TFET and proposed DG-JL-TFET: enhancing the RF performance through qualitative and quantitative approaches;Applied Physics A;2024-05-06

2. Enhancing Performance and Versatility of DG-JL-TFET with A1N Piezoelectric Materials for High-Power Applications;2024 International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI);2024-04-17