High speed sample and hold design using closed-loop pole-zero cancelation-Reference-Cited by-同舟云学术

High speed sample and hold design using closed-loop pole-zero cancelation

Published:2011-12 Issue:12 Volume:42 Page:1353-1358
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Arash Mirhaj S.,Norouzpour-Shirazi Arashk,Jafarabadi-Ashtiani Shahin,Shoaei Omid

Publisher

Elsevier BV

Subject

General Engineering

Reference11 articles.

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4. Cheng-Chung Hsu, Jieh-Tsorng Wu. A CMOS 33mW 100MHz 80dB SFDR sample-and-hold amplifier. Digest of Technical Papers Symposium on VLSI Circuits, 2003, pp. 263–266.

5. A novel low power 1 GS/s S&H architecture with improved analog bandwidth;Norouzpour-Shirazi;IEEE Trans. Circuits Syst. Express Briefs,2008

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