Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devices-Reference-Cited by-同舟云学术

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Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devices

Published:2016-01 Issue: Volume:362 Page:483-489
ISSN:0169-4332
Container-title:Applied Surface Science
language:en
Short-container-title:Applied Surface Science

Author:

Meng Lingkuan,Hong Peizhen,He Xiaobin,Li Chunlong,Li Junjie,Li Junfeng,Zhao Chao,Wei Yayi,Yan Jiang

Funder

Chinese National Science and Technology Major Project

Publisher

Elsevier BV

Subject

Surfaces, Coatings and Films,Condensed Matter Physics,Surfaces and Interfaces,General Physics and Astronomy,General Chemistry

Reference15 articles.

1. Proc. Technical Digest of International Electron Device Meeting;Veloso,2009

2. VLSI Symp. Tech. Dig.;Shang,2006

3. VLSI Symp. Tech. Dig.;van Dal,2007

4. VLSI Symp. Tech. Dig.;Auth,2012

5. International Electron Devices Meeting Tech. Dig.;Keshavarzi,2011

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