Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

Author:

LI Zhen-rong,ZHUANG Yi-qi,ZHANG Chao,JIN Gang

Publisher

Elsevier BV

Subject

Computer Networks and Communications,Information Systems,Signal Processing

Reference16 articles.

1. ZigBee Specification Version 1.0;ZigBee,2004

2. IEEE 802.15.4—2006. IEEE standard for information technology—Telecommunications and information exchange between system—Local and metropolitan area networks specific requirements, Part 15.4: Wireless MAC and physical layer (PHY) specifications for low-rat wireless personal area networks (LR-WPANs). 2006.

3. Federal Information Processing Standards (FIPS) 197. Specification for the advanced encryption standard (AES). 2001.

4. Kosaraju NM, Varanasi M, Mohanty SP. A high-performance VLSI architecture for advanced encryption standard (AES) algorithm. Proceedings of 19th International Conference on VLSI Design, Held with the 5th International Conference on Embedded Systems and Design, Jan 3–7, 2006, Hyderabad, India. Los Alamitos, CA, USA: IEEE Computer Society, 2006: 4.

5. Alam M, Ray S, Mukhopadhayay D, et al. an area optimized reconfigurable encryptor for AES-rijndael. Proceedings of Design, Automation & Test in Europe Conference & Exhibition, Apr 16–20, 2007. Nice, France. Piscataway, NJ, USA: IEEE, 2007: 1– 6.

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