A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm
Author:
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
http://www.tandfonline.com/doi/pdf/10.1080/00207217.2013.775626
Reference21 articles.
1. A new VLSI implementation of the AES algorithm
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3. Computational Approach for Securing Radiology-Diagnostic Data in Connected Health Network using High-Performance GPU-Accelerated AES;Interdisciplinary Sciences: Computational Life Sciences;2016-01-11
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