The Tag Filter Architecture: An energy-efficient cache and directory design

Author:

Valls Joan J.,Ros Alberto,Gómez María E.,Sahuquillo JulioORCID

Funder

European Regional Development Fund

Fundación Séneca

European Commission

Ministerio de Economía y Competitividad

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference37 articles.

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2. D.H. Albonesi, Selective cache ways: On-demand cache resource allocation, in: 32nd IEEE/ACM Int’l Symp. on Microarchitecture, MICRO, 1999, pp. 248–259.

3. Multi-Core Cache Hierarchies, Synthesis Lectures on Computer Architecture;Balasubramonian,2011

4. C. Bienia, S. Kumar, J.P. Singh, K. Li, The PARSEC benchmark suite: Characterization and architectural implications, in: 17th Int’l Conf. on Parallel Architectures and Compilation Techniques, PACT, 2008, pp. 72–81.

5. B. Calder, D. Grunwald, Predictive sequential associative cache, in: 2nd Int’l Symp. on High-Performance Computer Architecture, HPCA, 1996, pp. 244–253.

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