Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags

Author:

Rostami-Sani Sajjad1,Valinataj Mojtaba1ORCID,Chamazcoti Saeideh Alinezhad1

Affiliation:

1. Department of Electrical and Computer Engineering, Babol Noshirvani University of Technology, Shariati Ave., Postal Code: 47148-71167, Babol, Mazandaran, Iran

Abstract

The cache system dissipates a significant amount of energy compared to the other memory components. This will be intensified if a cache is designed with a set-associative structure to improve the system performance because the parallel accesses to the entries of a set for tag comparisons lead to even more energy consumption. In this paper, a novel method is proposed as a combination of a counting Bloom filter and partial tags to mitigate the energy consumption of set-associative caches. This new hybrid method noticeably decreases the cache energy consumption especially in highly-associative instruction caches. In fact, it uses an enhanced counting Bloom filter to predict cache misses with a high accuracy as well as partial tags to decrease the overall cache size. This way, unnecessary tag comparisons can be prevented and therefore, the cache energy consumption is considerably reduced. Based on the simulation results, the proposed method provides the energy reduction from 22% to 31% for 4-way–32-way set-associative L1 caches bigger than 16[Formula: see text]kB running the MiBench programs. The improvements are attained with a negligible system performance degradation compared to the traditional cache system.

Funder

the funding support of Babol Noshirvani University of Technology

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. DM-Pages: Improving Energy Efficiency of Disk Storage Systems and Cache Performance Using Deduplication-Based Mixed Pages;Journal of Circuits, Systems and Computers;2022-06-18

2. A New Prefetching Unit for Digital Signal Processor;Proceeding of 2021 International Conference on Wireless Communications, Networking and Applications;2022

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