DSPONE48: A methodology for automatically synthesize HDL focus on the reuse of DSP slices-Reference-Cited by-同舟云学术

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DSPONE48: A methodology for automatically synthesize HDL focus on the reuse of DSP slices

Published:2017-08 Issue: Volume:106 Page:132-142
ISSN:0743-7315
Container-title:Journal of Parallel and Distributed Computing
language:en
Short-container-title:Journal of Parallel and Distributed Computing

Author:

De Lucas Enrique,Sanchez-Elez Marcos^ORCID,Pardines Inmaculada

Funder

Spanish grant

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference28 articles.

1. Architectural modifications to enhance the floating-point performance of FPGAs;Beauchamp;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2008

2. Benchmarks ITC99. http://www.cad.polito.it/downloads/tools/itc99.html.

3. Catapult synthesis: A practical introduction to interactive C synthesis;Bollaert,2010

4. The iDEA DSP block-based soft processor for FPGAs;Cheah;ACM Trans. Reconfigurable Technol. Syst.,2014

5. A Survey of High Level Sunthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing;Daoud,2014

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1. FLIA: Architecture of Collaborated Mobile GPU and FPGA Heterogeneous Computing;Electronics;2022-11-16

2. Guest Editorial: Special Issue on Reconfigurable Computing and FPGA Technology;Journal of Parallel and Distributed Computing;2019-11

3. FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach;International Journal of Reconfigurable Computing;2019-04-01

4. An Efficient Method of Parallel Multiplication on a Single DSP Slice for Embedded FPGAs;IEEE Access;2019

5. FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method;International Journal of Reconfigurable Computing;2018

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