A new floating-point adder FPGA-based implementation using RN-coding of numbers-Reference-Cited by-同舟云学术

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A new floating-point adder FPGA-based implementation using RN-coding of numbers

Published:2021-03 Issue: Volume:90 Page:106947
ISSN:0045-7906
Container-title:Computers & Electrical Engineering
language:en
Short-container-title:Computers & Electrical Engineering

Author:

Araujo Túlio^ORCID,Cardoso Matheus B.R.^ORCID,Nepomuceno Erivelton G.,Llanos Carlos H.^ORCID,Arias-Garcia Janier^ORCID

Funder

Pró-Reitoria de Pesquisa, Universidade Federal de Minas Gerais

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference25 articles.

1. What every computer scientist should know about floating-point arithmetic;Goldberg;ACM Comput Surv,1991

2. Handbook of floating-point arithmetic;Muller,2010

3. IEEE Standard for Floating-Point Arithmetic;Institute of Electrical and Electronics Engineers (IEEE),2019

4. Some issues related to double roundings;Martin-Dorel,2011

5. Contributions to floating-point arithmetic : Coding and correct rounding of algebraic functions;Panhaleux,2012

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1. Exploring Temperature, Power, and Hardware Utilization in Half Adder Implementation on FPGA Platforms;2024 2nd International Conference on Sustainable Computing and Smart Systems (ICSCSS);2024-07-10

2. Area-latency efficient floating point adder using interleaved alignment and normalization;Microprocessors and Microsystems;2023-06

3. A New Chaos-Based PRNG Hardware Architecture Using the HUB Fixed-Point Format;IEEE Transactions on Instrumentation and Measurement;2023

4. Compact MAX and MIN Stochastic Computing architectures;Integration;2022-11

5. A Simple Numerical Solution Framework for Ordinary Differential Equations Based on Reduced MIPS Instructions;2022 IEEE 4th International Conference on Circuits and Systems (ICCS);2022-09-23

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