Area-latency efficient floating point adder using interleaved alignment and normalization

Author:

Pitchai Senthil,Pitchai Saravanan

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference30 articles.

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3. High-Speed FPGA Implementation of SIKE based on an ultra-low-latency modular multiplier;Tian;IEEE Trans. Circuits Syst. I: Reg. Papers,2021

4. Reliable CRC-based error detection constructions for finite field multipliers with applications in cryptography;Canto;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2021

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1. Fixed-point Encoding and Architecture Exploration for Residue Number Systems;ACM Transactions on Architecture and Code Optimization;2024-09-14

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