A high level power model for Network-on-Chip (NoC) router-Reference-Cited by-同舟云学术

A high level power model for Network-on-Chip (NoC) router

Published:2009-11 Issue:6 Volume:35 Page:837-845
ISSN:0045-7906
Container-title:Computers & Electrical Engineering
language:en
Short-container-title:Computers & Electrical Engineering

Author:

Lee Seung Eun,Bagherzadeh Nader

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference27 articles.

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3. Woo SC, Ohara M, Torrie E, Singh JP, Gupta A. The splash-2 programs: characterization and methodological considerations. In: ISCA’95: Proceedings of the 22nd annual international symposium on computer architecture; 1995. p. 24–36.

4. Patel C, Chai S, Yalamanchili S, Schimmel D. Power constrained design of multiprocessor interconnection networks. In: ICCD’97: Proceedings of the 1997 international conference on computer design (ICCD’97); 1997. p. 408–16.

5. Wang H, Zhu X, Peh L-S, Malik S. Orion: a power-performance simulator for interconnection networks. In: MICRO; 2002. p. 294–305.

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