A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip
Author:
Affiliation:
1. Graduate School of Information Science and Technology, The University of Tokyo
2. Department of Computer Science, Columbia University
3. Graduate School of Information Systems, The University of Electro-Communications
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software
Link
https://www.jstage.jst.go.jp/article/transinf/E99.D/12/E99.D_2016PAP0026/_pdf
Reference30 articles.
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3. [3] R. Mullins, A. West, and S. Moore, “Low-latency virtual-channel routers for on-chip networks,” Proc. 31st ISCA, pp.188-197, June 2004.
4. [4] H. Matsutani, M. Koibuchi, H. Amano, and T. Yoshinaga, “Prediction router: A low-latency on-chip router architecture with multiple predictors,” IEEE Trans. Comput., vol.60, no.6, pp.783-799, 2011.
5. [5] Y. He, H. Sasaki, S. Miwa, and H. Nakamura, “Predict-more router: A low latency NoC router with more route predictions,” Proc. 27th IPDPSW, pp.842-850, May 2013.
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