BUTHA: Boost Up Clock Terminal with Heuristic Approach for NoC

Abstract

In recent days, there has been a growing interest in network-on-chip (NoC), as it offers a promising architecture for future systems on-chip (SoC). The performance degradation is the major problem in designing NoC, due to the complexity in designing a traffic generator and traffic estimator (TE) modules. In the conventional NoC design, new traffic modules and low-power algorithms (LPAS) are introduced. A LPA with an NoC has given performance degradation in the transmission rate, end-to-end delay and overall energy consumption. To address this power issue, we modeled the Menger’s theorem (MT) (graph theory (GT))-based clock boosting mechanism to produce an effective frequency for the router. The following two methods are introduced to improve the performance of NoCs: (i) development of a real-time traffic generation module and software-based traffic estimator (STE) (ii) GT approach is introduced into a dynamic frequency scaling (DFS) LPA. In general, the frequency selection process during various traffic conditions in history-based dynamic voltage scaling algorithm (HDVS) and history-based DFS algorithm (HDFS) is more complex and it gives performance degradation. In the proposed method, MT-based DFS (MT-DFS) parameters are estimated under various conditions using both 65 and 90[Formula: see text]nm TSMC CMOS technology. In comparison with conventional HDFS, the evaluations show that MT-DFS interface achieves 67.7% energy saving, 85% dynamic power savings of the links in the on-chip network and 74.27% leakage power saving of the link.