1. Z. Huang. High-level Optimization Techniques for Low-Power Multiplier Design. Los Angeles, CA: University of California, 2003.
2. Minimization of switching activities of partial products for designing low-power multipliers
3. Low power multipliers based on new hybrid full adders
4. Study implementation and comparison of different multipliers based on array KCM and vedic mathematics using EDA tools;Ali M. H.;Int. J. Sci. Rese Publicat.,2013
5. A review on reversible logic gates and their implementation;Garipelly R.;Int. J. Emerg. Techn. Advan. Eng.,2013