A high performance processor architecture for multimedia applications-Reference-Cited by-同舟云学术

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A high performance processor architecture for multimedia applications

Published:2018-02 Issue: Volume:66 Page:14-29
ISSN:0045-7906
Container-title:Computers & Electrical Engineering
language:en
Short-container-title:Computers & Electrical Engineering

Author:

Khan Shafqat,Rashid Muhammad,Javaid Faraz

Funder

KACST

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference29 articles.

1. Capability hardware enhanced RISC instructions: CHERI instruction-set architecture (version 6);Watson,2017

2. Application specific processors for multimedia applications;Rashid,2008

3. Evaluation of ASIPs design with LISATek;Rashid,2008

4. A proposed RISC instruction-set architecture for the MAC unit of 32-bit VLIW DSP processor core;Huu,2014

5. Re-configurable SWP operator for multimedia processing;Khan,2009

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3. Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA;IEEE Access;2020

4. An Optimization Framework for Codes Classification and Performance Evaluation of RISC Microprocessors;Symmetry;2019-07-19

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