Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA-Reference-Cited by-同舟云学术

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

Published:2020 Issue: Volume:8 Page:172996-173007
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Qui Nguyen My^ORCID,Lin Chang Hong^ORCID,Chen Poki^ORCID

Funder

Ministry of Science and Technology (MOST), Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

http://xplorestaging.ieee.org/ielx7/6287639/8948470/09200617.pdf?arnumber=9200617

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