Error Detection of Data Conversion in Flash ADC using Code Width Based Technique

Author:

Senthil Sivakumar M,Gurumekala T,Pulya Sruthi

Publisher

Elsevier BV

Subject

General Engineering

Reference18 articles.

1. Alaa Abualsaud, Saeed Mian Qaisar, Zainab Al-Sheikh, Mohammad Akbar. (2016), “Design and Implementation of a 5-Bit Flash ADC for education”, IEEE 5th International Conference on Electronic Devices, Systems and Applications: 1-4. doi: 10.1109/ICEDSA.2016.7818471.

2. Barragan;Renaud;“A 65nm CMOS ramp generator design and its application towards a BIST implementation of the reduced-code static linearity test technique for pipeline ADCs”, Journal Electron Test,2016

3. “An area efficient, high-frequency digital built-in self-test for analog to digital converter”;Sivakumar;International Journal Electronics,2018

4. Barua, A, Tausiff, M. (2011) “Code width built-in self-test circuit for 8-bit pipelined ADC”. IEEE 21st International Conference on Systems Engineering: 287-291.

5. “Design and analysis of a bootstrap ramp generator circuit based on a bipolar junction transistor (BJT) differential pair amplifier”;Taissir;World congress conference on Engineering and Computer Science,2014

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1. An Accurate and Fast Method for Improving ADC Nonlinearity;Applied Computational Intelligence and Soft Computing;2023-09-15

2. Advanced Architecture of Analog to Digital Converter Derived from Half Flash ADC;Lecture Notes in Electrical Engineering;2022

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