FPGA Based Multiple Fault Tolerant and Recoverable Technique Using Triple Modular Redundancy (FRTMR)

Author:

Anjankar Shubham C.,Kolte Mahesh T.,Pund Ajinkya,Kolte Pratiksha,Kumar Ankita,Mankar Pranav,Ambhore Kunal

Publisher

Elsevier BV

Subject

General Engineering

Reference20 articles.

1. Kashif Sagheer Siddiqui, Mirza Altamash Baig. FRAM based TMR (Triple Modular Redundancy) for Fault Tolerance implementation. Proceedings of The Sixth IEEE International Conference on Computer and Information Technology (CIT’06), 2005.

2. Wei Chen, Rui Gong, Fang Liu, Kui Dai, Zhiying Wang. Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy. Proceedings International Conference on Dependable Systems and Networks, pp. 389-98, 23-26 June 2006.

3. Mark Hunger and Sybille Hellebrand. The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, (2010).

4. Chris Winstead, Yi Luo, Eduardo Monzon, and Abiezer Tejeda. An error correction method for binary and multiple-valued logic. 41st IEEE International Symposium on Multiple-Valued Logic, 2011.

5. Jun Yao, Ryoji Watanabe, Kazuhiro Yoshimura, Takashi Nakada, Hajime Shimada, and Yasuhiko Nakashima. An Efficient and Reliable 1.5-way Processor by Fusion of Space and Time Redundancies. IEEE TRANSACTION, 2011.

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