An Error Correction Method for Binary and Multiple-Valued Logic
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5952386/5954199/05954217.pdf?arnumber=5954217
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Fault Tolerance in Carbon Nanotube Transistors Based Multi Valued Logic;Carbon Nanotubes - Redefining the World of Electronics;2021-10-13
2. Real-Time FPGA-Based Fault Tolerant and Recoverable Technique for Arithmetic Design Using Functional Triple Modular Redundancy (FRTMR);Proceedings of the Second International Conference on Computational Intelligence and Informatics;2018
3. Improving the Performance of the Carrier Tracking Loop for GPS Receivers in Presence of Transient Errors due to PVT Variations;2016 IEEE International Workshop on Signal Processing Systems (SiPS);2016-10
4. CNTFET-RFB: An Error Correction Implementation for Multi-valued CNTFET Logic;2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL);2016-05
5. FPGA Based Multiple Fault Tolerant and Recoverable Technique Using Triple Modular Redundancy (FRTMR);Procedia Computer Science;2016
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