Configurable digit-serial convolver of type F

Author:

Milentijević Ivan Z.,Stojčev Mile K.,Maksimović Dejan M.

Publisher

Elsevier BV

Subject

General Engineering

Reference8 articles.

1. Why systolic architectures;Kung;IEEE Computer,1982

2. Serial/parallel convolvers;Danielsson;IEEE Trans. Computers,1984

3. Semi-systolic maximum rate transversal filters with programmable coefficients;Noll,1986

4. A configurable convolution chip with programmable coefficients;Reurer;IEEE J. Solid-State Circuits,1992

5. A digit-serial processing technique;Hartley;IEEE Trans. Circuits Syst.,1990

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1. Configurable folded array for FIR filtering;Journal of Systems Architecture;2008-01

2. FPGA implementation of folded FIR filter architecture with changeable folding factor;Facta universitatis - series: Electronics and Energetics;2002

3. Mixed-signal modeling with AleC++: Specific features of the HDL;Simulation Practice and Theory;2001-03

4. Matrix-vector multiplication on a fixed-size linear systolic array;Computers & Mathematics with Applications;2000-11

5. Folded bit-plane FIR filter architecture with changeable folding factor;Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

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