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Configurable folded array for FIR filtering

  • Published:2008-01 Issue:1-2 Volume:54 Page:177-196
  • ISSN:1383-7621
  • Container-title:Journal of Systems Architecture
  • language:en
  • Short-container-title:Journal of Systems Architecture

Author:

Ciric Vladimir,Milentijevic Ivan

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference18 articles.

1. Reconfiguring wireless phones with adaptive chips;Paulson;IEEE Computer,2003

2. Adaptive deblocking filter;List;IEEE Transactions on Circuits and Systems for Video Technology,2003

3. Video deblocking with fine-grained scalable complexity for embedded mobile computing;Yu;International Conference on Signal Processing,2004

4. H.264 and MPEG-4 Video Compression – Video Coding for Next Generation Multimedia;Richardson,2003

5. A configurable convolution chip with programmable coefficients;Reuver;IEEE Journal of Solid State Circuits,1992

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A novel implementation of combined systolic and folded architectures for adaptive filters in FPGA;Microprocessors and Microsystems;2020-04

2. Tropical algebra based framework for error propagation analysis in systolic arrays;Applied Mathematics and Computation;2013-12

3. Yield analysis of partial defect tolerant bit-plane array;Computers & Mathematics with Applications;2010-01

4. Partial error tolerance for bit-plane FIR filter architecture;AEU - International Journal of Electronics and Communications;2009-05

5. Error significance map for bit-plane FIR filtering array;2008 26th International Conference on Microelectronics;2008-05
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