A back-gate bias effect model considering the charge accumulation behavior above the field oxide for ultra-thin SOI NMOS devices
Author:
Publisher
Elsevier BV
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference11 articles.
1. Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's
2. VB-6 Charge-based large-signal modeling of thin-film SOI MOSFET's
3. Substrate bias dependence of subthreshold slopes in fully depleted silicon-on-insulator MOSFET's
4. An analytical model for back-gate effects on ultrathin-film SOI MOSFET's
5. A temperature-dependent SOI MOSFET model for high-temperature application (27 degrees C-300 degrees C)
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Modeling narrow-channel effect in VLSI mesa-isolated SOI MOS devices using a quasi-two-dimensional approach;Solid-State Electronics;1996-09
2. A DC model for fully-depleted SOI MOSFETs;International Journal of Electronics;1995-09
3. Simulation of the transient characteristics of partially- and fully-depleted SOI MOSFETs;Solid-State Electronics;1994-07
4. An analytical delayed-turn-on model for accumulation-type ultra-thin SOI PMOS devices operating at 77 K;Solid-State Electronics;1994-03
5. The delayed-turn-on behavior in the accumulation-type SOI PMOS device operating at 77 K;Solid-State Electronics;1993-05
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