A fault tolerant massively parallel processing architecture-Reference-Cited by-同舟云学术

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A fault tolerant massively parallel processing architecture

Published:1987-08 Issue:4 Volume:4 Page:363-383
ISSN:0743-7315
Container-title:Journal of Parallel and Distributed Computing
language:en
Short-container-title:Journal of Parallel and Distributed Computing

Author:

Balasubramanian Vijay,Banerjee Prithviraj

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference14 articles.

1. Reconfigurable cube-connected cycles architectures;Banerjee,1986

2. The ILLIAC IV computer;Barnes;IEEE Trans. Comput.,1968

3. A fault-tolerant architecture for network storage systems;Grey,1984

4. MAN-YO: A special purpose parallel machine for logic design automation;Koike,1985

5. A reconfigurable and fault-tolerant VLSI multiprocessor array;Koren,1981

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Characterization, testing and reconfiguration of faults in mesh networks;Integration;2007-07

2. On Fault Tolerance of Two-Dimensional Mesh Networks;Distributed Computing and Networking;2006

3. On characterization of catastrophic faults in two-dimensional VLSI arrays;Integration;2004-12

4. Characterization of catastrophic faults in two-dimensional reconfigurable systolic arrays with unidirectional links;Information Processing Letters;2004-11

5. Reliability of VLSI Linear Arrays with Redundant Links;Distributed Computing - IWDC 2004;2004

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