1. Balasubramanian, V., Banerjee, P.: A fault tolerant massively parallel processing architechture. Journal of Parallel and Distributed Computing 4, 363–383 (1987)
2. Bruck, J., Cypher, R., Ho, C.T.: Fault-tolerant meshes with minimal number of spares. In: Proc. of 3rd IEEE Symposium on Parallel and Distributed Processing, pp. 288–295 (1991)
3. De Prisco, R., Monti, A., Pagli, L.: Efficient testing and reconfiguration of VLSI linear arrays. Theoretical Computer Science 197, 105–129 (1998)
4. De Prisco, R., De Santis, A.: Catastrophic faults in reconfigurable systolic linear arrays. Discrete Applied Math. 75, 105–123 (1997)
5. Cormen, T.H., Lierson, C.E., Rivest, R.L., Stein, C.: Introduction to Algorithms. MIT Press, Cambridge