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Design optimization of stacked layer dielectrics for minimum gate leakage currents

  • Published:2000-12 Issue:12 Volume:44 Page:2165-2170
  • ISSN:0038-1101
  • Container-title:Solid-State Electronics
  • language:en
  • Short-container-title:Solid-State Electronics

Author:

Zhang J,Yuan J.S,Ma Y,Oates A.S

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference12 articles.

1. Iwai H, Momose HS. Ultra-thin gate oxes – performance and reliability. Proc IEDM 1998. No. 7-1

2. Zhang J, Yuan JS, Ma Y, Oates AS. Direct tunneling and surface roughness effects on C–V characteristics of ultrathin gate CMOS, unpublished data

3. Reaction/annealing pathways for forming ultrathin silicon nitre films for composite oxide nitre gate dielectrics with nitrided crystalline silicon-dielectric interfaces for application in advanced complementary MOS devices;Lucovsky;J Vac Sci Technol A,1999

4. Making silicon nitre film a viable gate dielectric;Ma;IEEE Trans Electron Dev,1998

5. Generalized formula for the electric tunnel effect between similar electrodes separated by a thin insulating film;Simmons;J Appl Phys,1963

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