Two-level pipelined systolic arrays for matrix-vector multiplication-Reference-Cited by-同舟云学术

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Two-level pipelined systolic arrays for matrix-vector multiplication

Published:1998-02 Issue:5 Volume:44 Page:383-387
ISSN:1383-7621
Container-title:Journal of Systems Architecture
language:en
Short-container-title:Journal of Systems Architecture

Author:

Milentijević Ivan Z.,Milovanović Igor Z.,Milovanović Emina I.,Tošić Milorad B.,Stojčev Mile K.

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference4 articles.

1. Systolic arrays for VLSI;Kung,1980

2. Optimizing systolic networks by fitting diagonals;Suros;Parallel Comput.,1987

3. The fastest matrix-vector multiplication;Gusev;Parallel Algorith. Appl.,1993

4. Fault-Tolerance through Reconfiguration of VLSI and WSI Arrays;Negrini,1989

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Exploiting inter-operation parallelism for matrix chain multiplication using MapReduce;The Journal of Supercomputing;2013-04-20

2. FPGA implementation of folded FIR filter architecture with changeable folding factor;Facta universitatis - series: Electronics and Energetics;2002

3. Matrix-vector multiplication on a fixed-size linear systolic array;Computers & Mathematics with Applications;2000-11

4. Data reordering converter: an interface block in a linear chain of processing arrays;Microelectronics Journal;2000-01

5. Folded bit-plane FIR filter architecture with changeable folding factor;Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

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