Design of quaternary MIN and MAX circuits using graphene nanoribbon field effect transistors

Author:

Javid Basha Shaik,Venkatramana P

Publisher

Elsevier BV

Subject

General Medicine

Reference22 articles.

1. Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs;Liang;IEEE Trans. Nanotechnol.,2014

2. Design and comparative analysis of binary and quaternary logic circuits;Dawley;World Conf. Futur. Trends Res. Innov. Social Welf. (Startup Conclave),2016

3. V. Patel K.S. and K. S. Gurumurthy, “Design of High Performance Quaternary Adders,”2011 41st IEEE International Symposium on Multiple-Valued Logic, 2011, pp. 22-26

4. Quaternary multiplier circuit;Chu,1994

5. A CMOS quaternary-to-binary logic decoder;Beom Kim,2008

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1. A novel quaternary inward inverter gate based on MIN and MAX functions;International Journal of Electronics;2024-09-08

2. Quaternary MIN Logic Gate with Ballistic Graphene Devices;2024 IEEE 24th International Conference on Nanotechnology (NANO);2024-07-08

3. Conditional spatial transition reduction data encoding technique for VLSI interconnects;e-Prime - Advances in Electrical Engineering, Electronics and Energy;2024-03

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5. High-performance ternary designs using graphene nanoribbon transistors;Materials Today: Proceedings;2023-07

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