Implementation and comparative analysis of full-adders using 180 nm, 90 nm, and 45 nm technology in cadence

Author:

Spoorthi S.P.

Publisher

Elsevier BV

Subject

General Medicine

Reference10 articles.

1. Manjunath K M, Abdul Lateef Haroon P S, Amarappa Pagi, Ulaganathan J, “Analysis of various Full-Adder Circuits in Cadence”. International conference on Emerging Research in Electronics, Computer science and Technology -2015.

2. Raghavendra Singh, Shyam Akashe, “New High-Performance Low Power 4bit Full Adder with Reduce Ground Bounce Noise”. International Conference on Advanced Electronic Systems (ICAES)-2013.

3. P.A. Irfan Khan, Ravi Shankar Mishra, Sandeep Dhariwal ,“Comparative Analysis of Different Types of Full Adders using 180nm and 90nm Technology”. International Conference on Advances in Emerging Technology -2016.

4. Senthil Kumaran Varadharajan, Viswanathan Nallasamy, “Low Power VLSI Circuits Design Strategies and Methodologies: A Literature Review”. IEEE Conference on Emerging Devices and Smart Systems (ICDSS 2017) 3-4 March 2017.

5. Arvind Nigam, Raghavendra Singh, “Comparative analysis of 28T full adder with 14T full adder using 180nm”, Intl J Engg Sci Adv Research 2016 March.

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1. Design of Low-Power 10-Transistor Full Adder Using GDI Technique for Energy-Efficient Arithmetic Applications;Circuits, Systems, and Signal Processing;2023-01-07

2. HIGH-EFFICIENT VLSI ARCHITECTURE FOR THREE OPERAND BINARY ADDER;international journal of engineering technology and management sciences;2023

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