Author:
Varadharajan Senthil Kumaran,Nallasamy Viswanathan
Cited by
18 articles.
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1. A Novel 1-bit Fast and Low Power 17-T Full Adder Circuit;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24
2. Design of Full Adder Circuits with Optimized Power and Speed Using CMOS Technique;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24
3. A Novel 1-bit Fast and Low Power 19-T Full Adder Circuit at 45 nm Technology Node;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24
4. Current Crafting: Mastering Low-Power Configuration Methods;2023 International Conference on Next Generation Electronics (NEleX);2023-12-14
5. Implementing Logical Shifters: For Funtionality Testing and Performance of Power Analysis;2023 3rd Asian Conference on Innovation in Technology (ASIANCON);2023-08-25