Victim retention for reducing cache misses in tiled chip multiprocessors-Reference-Cited by-同舟云学术

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Victim retention for reducing cache misses in tiled chip multiprocessors

Published:2014-06 Issue:4 Volume:38 Page:263-275
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Das Shirshendu,Kapoor Hemangee K.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference38 articles.

1. Multi-Core Cache Hierarchies;Balasubramonian,2011

2. Introduction to the cell multiprocessor;Kahle;IBM J. Res. Dev.,2005

3. AMD Athlon 64 X2 dual-core processor for desktop. .

4. Intel. quad-core intel xeon processor 5400 series, April 2008. .

5. Intel teraflops machine. .

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1. A Two-Level Cache Aware Adaptive Data Replication Mechanism for Shared LLC;IEICE Transactions on Information and Systems;2022-07-01

2. A perceptron-based replication scheme for managing the shared last level cache;Microprocessors and Microsystems;2021-09

3. Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System;ACM Transactions on Design Automation of Electronic Systems;2020-05-14

4. Cache Memory Architectures for Handling Big Data Applications: A Survey;Advances in Intelligent Systems and Computing;2019-12-01

5. A Reuse-Degree Based Locality Classifier for Locality-Aware Data Replication;IEEE Access;2019

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