A Two-Level Cache Aware Adaptive Data Replication Mechanism for Shared LLC-Reference-Cited by-同舟云学术

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A Two-Level Cache Aware Adaptive Data Replication Mechanism for Shared LLC

Published:2022-07-01 Issue:7 Volume:E105.D Page:1320-1324
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

WU Qianqian¹,JI Zhenzhou¹

Affiliation:

1. School of Computer Science and Technology, Harbin Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E105.D/7/E105.D_2022EDL8002/_pdf

Reference12 articles.

1. [1] S. Das and H.K. Kapoor, “Victim retention for reducing cache misses in tiled chip multiprocessors,” Microprocess and Microsystem, vol.38, no.4, pp.263-275, 2014. 10.1016/j.micpro.2013.11.005

2. [2] M. Zhang and K. Asanovic, “Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors,” IEEE International Symposium on Computer Architecture, pp.336-345, IEEE, 2005. 10.1109/isca.2005.53

3. [3] B.M. Beckmann, M.R. Marty, and D.A. Wood, “ASR: adaptive selective replication for cmp caches,” International Symposium on Microarchitecture, pp.443-454, IEEE, 2006. 10.1109/micro.2006.10

4. [4] G. Kurian, S. Devadas, and O. Khan, “Locality-aware data replication in the last-level cache,” International Symposium on High-Performance Computer Architecture, pp.1-12, IEEE, 2014. 10.1109/hpca.2014.6835921

5. [5] P.A. Tsai, N. Beckmann, and D. Sanchez, “Nexus: a new approach to replication in distributed shared caches,” International Conference on Parallel Architectures and Compilation Techniques, pp.166-179, IEEE, 2017. 10.1109/pact.2017.42

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