High speed and efficient area optimal ate pairing processor implementation over BN and BLS12 curves on FPGA

Author:

Sghaier AnissaORCID,Zeghid Medien,Ghammam Loubna,Duquesne Sylvain,Machhout Mohsen,Ahmed Hassan Yousif

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference41 articles.

1. Updating key size estimations for pairings;Barbulescu,2017

2. A one round protocol for tripartite Diffe-Hellman;Joux;J. Cryptol.,2004

3. Identity-based encryption from the weil pairing;Boneh,2001

4. Short signatures from the weil pairing;Boneh;J. Cryptol.,2004

5. A method for obtaining digital signatures and public-key cryptosystems;Rivest;Commun. ACM,1978

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1. High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08

2. Novel area-efficient and flexible architectures for optimal Ate pairing on FPGA;The Journal of Supercomputing;2023-08-18

3. A Test System Design for JESD204B Transmitter Controller Chip;Advances in Natural Computation, Fuzzy Systems and Knowledge Discovery;2022

4. Compact and Programmable yet High-Performance SoC Architecture for Cryptographic Pairings;2020 30th International Conference on Field-Programmable Logic and Applications (FPL);2020-08

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